RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
Hardware ArchitectureArtificial IntelligenceMachine Learning
Summary
The authors address the problem of predicting how fast digital circuits will work during their design phase, which is usually hard. They created RTL-Sequencer, a new method that turns circuit information into sequences using a systematic traversal, making it easier to analyze with sequence models. They also improved these models with techniques like shuffling and bidirectional learning to get better predictions. Their experiments show this approach works better than existing methods, helping designers optimize circuits earlier.
Authors
Ziyan Guo, Wenji Fang, Wenkai Li, Yuchao Wu, Shang Liu, Zhiyao Xie
Abstract
Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation. Existing graph-based methods struggle with limited receptive fields, high complexity, and a lack of signal directionality. We present RTL-Sequencer, a novel sequence-based paradigm that enables scalable RTL timing prediction via linearizing logic cones by breadth-first traversal and applying modern linear sequence models. Furthermore, sequence models are customized by four synergistic techniques, including sequence shuffling, bidirectional modeling, differentiable modeling, and a hybrid graph-sequence architecture. Extensive experiments demonstrate significant improvements of RTL-Sequencer over state-of-the-art baselines, advancing early-stage timing optimization.