Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis
Cryptography and SecurityHardware Architecture
Summary
The authors created Vogls, a special computer program that simulates hardware designs to help find security weaknesses before building the actual device. Unlike regular simulators, Vogls is faster and lets users pause and change the simulation at key moments without starting over, which helps analyze data leaks better. They tested Vogls on encryption hardware and showed it could quickly and accurately find secret keys through side-channel attacks. This makes it a useful tool for designing safer hardware.
Authors
Gijs Burghoorn, Ileana Buhan, Lejla Batina
Abstract
Designing hardware circuits resistant to side-channel attacks increasingly relies on simulation to predict device leakage before fabrication. Current functional verification simulators are designed for extended correctness-checking runs and are ill-suited for producing large numbers of short trace collections with slight input variants needed for side-channel analysis. We present Vogls: an open-source Verilog simulator built for side-channel analysis, that is the first simulator to combine compiled-code performance, full-timing simulation, and fine-grained control over the simulation state. Vogls simulates a timing annotated gate-level AES design 5.9 times faster than Icarus Verilog and is only 30% slower than Verilator on a PicoRV32 RTL design while also offering a more accurate timing model. Vogls provides a Python interface that allows simulations to be paused, forked, inspected, and mutated around points-of-interest without modifying the hardware design and thereby preserving timing and leakage characteristics. Furthermore, a trace-collection workflow runs setup code once and forks at the point-of-interest, eliminating the need to re-simulate from reset for every trace. A case study demonstrates Vogls on a differential power analysis attack that successfully recovers the key at RTL, GTL and full-timing GTL abstraction levels.