Soft-Error Characterization and Hardening Trade-offs in Static PCHB Asynchronous Circuits
2026-07-12 • Hardware Architecture
Hardware Architecture
AI summaryⓘ
The authors studied how a specific asynchronous circuit design called Pre-Charge Half Buffer (PCHB) handles soft errors caused by environmental disturbances. They created a method to inject faults at the transistor level to find weak spots in the circuit and measured how much charge causes errors. Then, the authors tested four ways to reduce errors, including special triggers and redundancy, across several PCHB designs. They compared each method's impact on speed, energy use, and size to provide guidelines for making PCHB circuits more reliable.
Pre-Charge Half Buffer (PCHB)asynchronous digital designsoft errorfault injectioncritical chargeSchmitt triggertransmission gateredundancycircuit hardeningresilience overhead
Authors
Ramya Karri, Srija Rasoori, Ashiq A. Sakib
Abstract
Pre-Charge Half Buffer (PCHB) is a promising asynchronous digital design paradigm for harsh-environment operation; however, its soft-error characteristics remain largely unexplored. This paper presents a systematic soft-error characterization and hardening trade-off analysis for static PCHB circuits. A controlled transistor-level fault-injection framework is developed to extract polarity-dependent critical charge at internal nodes. Vulnerability nodes are identified based on extensive simulation. Four mitigation strategies, double-sided Schmitt trigger, single-sided Schmitt trigger, transmission-gate reinforcement, and duplication-based redundancy, are implemented and evaluated across five representative PCHB cells. Comprehensive resilience-overhead comparisons in delay, energy, and area are reported, leading to architecture-specific hardening guidelines for robust static PCHB design.