HSF-S: Speed-Optimized Compilation and Acceleration for Hybrid Schrodinger-Feynman Quantum Circuit Emulation
2026-07-11 • Emerging Technologies
Emerging Technologies
AI summaryⓘ
The authors introduce HSF-S, a new system combining software and hardware optimizations to better simulate quantum circuits using a method called Hybrid Schrödinger-Feynman (HSF). Their approach rearranges quantum operations and inserts specific gates to reduce the costly parts of the simulation involving interactions across different sections. They also design a special processor to efficiently handle the simulation without needing huge memory. Testing on various circuits showed HSF-S keeps results accurate while making simulations up to 90% cheaper and much faster, sometimes bringing hours-long tasks down to seconds.
Quantum Circuit SimulationHybrid Schrödinger-FeynmanQuantum EmulatorCross-boundary Two-Qubit GatesCompiler OptimizationSWAP GatePath Cost ModelFPGA AcceleratorGPU SimulationQuantum State Vector
Authors
Sechan Park, Kyeongwon Lee, Mundo Jeong, Chaebin Jung, Woojoo Lee
Abstract
Hybrid Schrodinger-Feynman (HSF) simulation offers an attractive memory-path tradeoff for exact quantum-circuit emulation, but its practical runtime is often dominated by exponential path growth from cross-boundary two-qubit gates. Existing GPU and FPGA quantum simulators are largely optimized for full-state Schrodinger execution and therefore do not align well with HSF's path-centric workflow. This paper presents HSF-S, a compiler-accelerator co-designed framework for exact HSF-based quantum circuit emulation. HSF-S lowers input circuits to an HSF-compatible basis, formulates a rank-aware effective path-cost model, and applies dependency-preserving reordering together with discounted-gain SWAP insertion to suppress recurring cross-boundary interactions while preserving exact circuit semantics. A regression-free selector guarantees that the compiled circuit never increases effective path cost relative to the naive lowered baseline. We further design a dedicated HSF-S accelerator and execution flow, and integrate them into a stand-alone processor for efficient per-path dual-slice evaluation and final accumulation without materializing the full state vector. Across 56 benchmark circuits, HSF-S matches reference amplitudes to within floating-point precision, reduces effective path cost by up to 90.0%, and substantially improves practical tractability, including representative timeout-to-sub-second reductions under a 1-hour budget. On the resulting compiled workloads, the HSF-S processor prototype delivers up to 4.34x additional speedup.