High-Performance NTT Accelerators for PQC leveraging Unified Redundant Arithmetic and Fine-Tuned Microarchitecture
2026-07-01 • Hardware Architecture
Hardware ArchitectureCryptography and Security
AI summaryⓘ
The authors studied how to make certain math operations, important for future encryption methods resistant to quantum computers, run faster on specialized hardware. They focused on improving the Number Theoretic Transform (NTT), a crucial step in these math operations, by designing better hardware units and using a new way to represent numbers that avoids extra correction steps. Their improvements also combined some steps to save space and used a smart multiplier design suitable for FPGA chips. Tests showed their approach runs faster and uses hardware more efficiently, which can help with secure communication in the future.
Post-quantum cryptographyNumber Theoretic Transform (NTT)Montgomery multiplicationFPGACRYSTALS-KyberCRYSTALS-DilithiumPolynomial arithmeticModular reductionHardware acceleratorButterfly unit
Authors
George Alexakis, Dimitrios Schoinianakis, Giorgos Dimitrakopoulos
Abstract
Post-quantum cryptography and privacy-preserving technologies are expected to play a central role in future secure communication systems. Lattice-based PQC schemes such as ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium) rely heavily on large-degree polynomial arithmetic, making the Number Theoretic Transform (NTT) a key computational primitive. Although existing hardware accelerators exploit parallelism and pipelining to support both NTT and INTT, their efficiency is often limited by the overhead of modular reduction and correction steps, inverse-transform scaling operations, and suboptimal FPGA implementations. This work addresses these limitations by proposing parallel iterative NTT/INTT accelerators based on optimized unified butterfly units. We introduce a novel redundant number representation that eliminates conditional corrections for both Montgomery modulo multiplication and combined subtract-multiply operations, and integrate inverse-transform scaling into existing arithmetic hardware to avoid dedicated scaling units. Furthermore, we design hierarchical Montgomery multipliers that map efficiently onto FPGA DSP resources, reducing hardware cost while enabling high operating frequencies. FPGA-based experimental results demonstrate higher clock frequencies, reduced execution times, and competitive resource utilization, supporting efficient NTT acceleration for PQC and related privacy-preserving applications.