Mega: A 22 nm Convolutional Spiking Neural Network Accelerator Achieving 0.375 pJ/SOP for Efficient Edge Vision
2026-06-29 • Hardware Architecture
Hardware Architecture
AI summaryⓘ
The authors designed a new computer chip called Mega to make spiking neural networks (SNNs) better and more energy-efficient for vision tasks. Their chip works faster by handling many small 3x3 convolutions at once and uses one memory system for all the important data. They also improved how the chip detects and processes spikes, which are signals in SNNs. Tested in a modern 22 nm technology, Mega uses four times less energy than previous designs.
Spiking Neural NetworksConvolutional Neural NetworksEnergy Efficiency3x3 ConvolutionsSpike DetectionDigital ArchitectureMemory ArchitectureEvent-driven ComputationGlobalFoundries 22 nm FDSOISparsity
Authors
Rick Luiken, Manil Dev Gomony, Sander Stuijk
Abstract
Convolutional Spiking Neural Networks (SNN) offer the potential for highly energy-efficient vision processing by exploiting sparse, event-driven computation. However, existing SNN accelerators underutilize the inherent parallelism of convolutional layers and lack the flexibility to accommodate varying memory demands and input sparsity across layers. This paper presents Mega, a digital architecture for convolutional SNNs that addresses these limitations through three key contributions: (1) highly parallel acceleration of $3 \times 3$ convolutions, (2) a unified data memory for spikes, neuron states, and weights, and (3) efficient spike map processing with low-overhead spike detection. Fabricated in GlobalFoundries 22 nm FDSOI technology, Mega achieves an energy efficiency of 0.375 pJ/SOP, improving the state of the art by $4\times$.