An Open-Source LFSR-Based Stochastic Leaky Integrate-and-Fire Neuron in SkyWater 130 nm: Design, Stochastic Characterisation, and Rate Coding
2026-06-22 • Emerging Technologies
Emerging TechnologiesHardware ArchitectureNeural and Evolutionary Computing
AI summaryⓘ
The authors designed a small, configurable stochastic spiking neuron using standard CMOS technology that mimics brain-like behavior with randomness to reduce hardware needs and noise sensitivity. Their design uses a random number generator and a programmable table to decide when the neuron fires, controlled through simple registers. They tested the design in simulation, confirming its accuracy and performance, including how firing probabilities and timing behave. The neuron is compact, runs fast, and is openly available alongside a broader neuromorphic toolkit. These findings provide detailed pre-silicon validation for using randomness in efficient edge hardware neurons.
stochastic spiking neuronleaky integrate-and-firelinear-feedback shift registerBernoulli processneuromorphic hardwareTiny TapeoutCMOS standard-cellrate codingrefractory period
Authors
Poornima Kumaresan, Santhosh Sivasubramani
Abstract
Stochastic spiking neurons trade exact arithmetic for controlled randomness, lowering area and tolerating input noise, which suits event-driven edge hardware. We present a compact, configurable stochastic leaky integrate-and-fire neuron in standard-cell CMOS on the SkyWater 130 nm process, released openly. A 16-bit configurable-polynomial linear-feedback shift register drives an eight-entry programmable activation table that sets a Bernoulli firing probability, and a saturating 16-bit leaky integrator with a programmable threshold and a refractory period of zero to seven cycles produces the spike train. All parameters are set through a sixteen-register serial interface, and the neuron runs from parallel inputs or entirely from the register file. From a model checked bit-exact against the register-transfer code, the period is 65535 states for a maximal-length polynomial and 63 for the shipped default, the eight-bit comparison value is uniform over the full period, and the per-entry firing probability equals the table value divided by 256. We also characterise a property a system-level model would not expose: the comparator output is serially correlated at short lags, with a negative lobe near lag eight, because the compared byte shifts by one bit each cycle; subsampling every sixteen cycles restores whiteness. Rate-coding sweeps show monotonic control of the output rate by the input weight and the threshold, and the refractory period caps the rate at one spike per refractory-plus-one cycles. The neuron occupies about 10,600 square micrometres at 70 per cent utilisation on a single Tiny Tapeout tile, meets 50 MHz timing with positive margin, and passes eighteen directed cocotb tests at register-transfer and gate level. All results are pre-silicon, from simulation and the open flow. The neuron is an openly released companion to a four-block neuromorphic suite reported separately.