Code size reduction by advanced near addressing modes
2026-05-25 • Hardware Architecture
Hardware Architecture
AI summaryⓘ
The authors explain that real-time systems often use many global variables, which can be hard to access quickly because their addresses are too large for simple instructions. Other computer architectures solve this by using special ways to access nearby variables more efficiently. The paper explores different methods to add these efficient access methods to the RISC-V instruction set. The authors also tested how these changes affect the size of the code with various programs.
real-time systemsglobal variablesaddressing modesRISC-V ISAnear addressingcode sizeinstruction set architectureCPU architectureperformance optimization
Authors
Kajetan Nuernberger, Thomas Roecker, Gergely Fueto, Gabor Spaits, Horst Lehser
Abstract
To enable debugging and calibration of real time systems, which are in interaction with the real plant, the software used on those systems often has a huge number of global variables. The huge number of global variables exceed the range addressable relative to the global pointer. Therefore, addressing these variables normally needs two instructions. Other CPU architectures commonly used in the real time control systems domain address these by various near addressing modes. This results in significant code size reductions and performance boost. This paper discusses different variants to add such near addressing features to the RISC-V ISA. The impact on the code size is evaluated with different representative workloads.