Wave-Based Dispatch for Circuit Cutting in Hybrid HPC--Quantum Systems
2026-04-16 • Distributed, Parallel, and Cluster Computing
Distributed, Parallel, and Cluster Computing
AI summaryⓘ
The authors created a system called DQR that splits large quantum computing tasks into smaller pieces and manages these pieces independently. This helps supercomputers run quantum workloads more efficiently by using existing resource management tools and switching automatically between local and cloud quantum processors or simulators if problems occur. Their tests show that DQR speeds up execution and handles failures smoothly without restarting the whole process. Overall, the system helps combine quantum computing tasks into regular high-performance computing setups while staying flexible for future improvements.
Hybrid HPC-Quantum WorkloadsCircuit CuttingNoisy Intermediate-Scale Quantum (NISQ)Fragment SchedulingResource ManagementQuantum Processing Units (QPUs)SupercomputingHardware-Efficient Ansatz (HEA)Task FailoverPipeline Concurrency
Authors
Ricard S. García-Raigada, Josep Jorba, Sergio Iserte
Abstract
Hybrid High-performance Computing (HPC)-quantum workloads based on circuit cutting decompose large quantum circuits into independent fragments, but existing frameworks tightly couple cutting logic to execution orchestration, preventing HPC centers from applying mature resource management policies to Noisy Intermediate-Scale Quantum (NISQ) workloads. We present DQR (Dynamic Queue Router), a runtime framework that bridges this gap by treating circuit fragments as first-class schedulable units. The framework introduces a backend-agnostic fragment descriptor to expose structural properties without requiring execution layers to parse quantum code, a wave-based coordinator that achieves pipeline concurrency via non-blocking polling, and a production-ready implementation on the CESGA Qmio supercomputer integrating both QPUs local on-premises (Qmio) and remote cloud (IBM Torino) backends. Experiments on a 32-qubit Hardware-Efficient Ansatz (HEA) circuit demonstrate not only makespan improvements over a monolithic CPU baseline but also transparent per-fragment failover recovery-specifically rerouting tasks from the local QPU to classical simulators upon encountering hardware-level incompatibilities-without pipeline restart. For deeper circuits, the coordination residual accounts for only 5% of the total execution time, highlighting the framework's scalability. These results show that DQR enables HPC centers to integrate NISQ workloads into existing production infrastructure while preserving the flexibility to adopt improved cutting algorithms or heterogeneous backend technologies.