Papers for
industrial simulation engineers
Papers whose findings have a practical use for this group, as judged from the abstract. Open a paper to read what it means in practice.
Autoregressive pde model rollouts improved by event triggered corrections
Stabilizing Autoregressive PDE Foundation Model Rollouts with Event-Triggered Context Healing
Abstract: Autoregressive PDE foundation models enable fast full-field forecasting but accumulate errors as predicted states are recursively reused. We introduce Event-Triggered Context Healing (ETCH), which compares forecasts with measurements from 12 cylinder-surface pressure taps. When their discrepancy exceeds a threshold, pressure-conditioned hourglass diffusion transformers reconstruct the velocity--pressure context for subsequent predictions. On 43 RealPDEBench Cylinder trajectories, ETCH reduces velocity and pressure errors from 48.05 and 63.71% to 6.29 and 7.25% for DPOT, and from 74.97 and 76.91% to 5.16 and 6.84% for Poseidon-T, using the same reconstructors and threshold. For DPOT, correcting 14.56% of windows maintains errors close to reconstructing every window and supports average real-time forecasting and correction on an A100 GPU. These results show that sparse physical feedback stabilizes long autoregressive rollouts across PDE foundation models while reducing reconstruction cost.
TinyTC and PyTorch/Triton boost stencil computing on GPUs
Stencil Computation at the Intersection of AI and HPC
Abstract: Tensor compilers such as TinyTC and OpenAI Triton were originally developed for AI workloads, but the same tiling and memory abstractions can be applied to implement efficient high-order stencils for scientific and industrial applications. We demonstrate this for an 8th-order, 25-point acoustic stencil with boundary conditions over an a demanding-sized grid, targeting GPGPUs, where we compare the hardware-specialized TinyTC implementation with a portable PyTorch/Triton implementation. The target platforms for evaluation include Intel B70, B580, GPU MAX 1550, NVIDIA A100/RTX6000 Blackwell/H100, and AMD MI325x. For instance, on Battlemage B580 TinyTC reaches 15.6 Gpts/s versus 13.5 Gpts/s for PT/Triton under random initialization, while zero-initialized runs reach up to 35.8 Gpts/s due to hardware memory compression. Using roofline and memory-hierarchy profiling, we show that -as expected- performance is predominantly bandwidth-limited and that compiler-managed L1/LSC caching can effectively replace programmer-managed shared-memory staging for this stencil class. Overall, the results position TinyTC as the performance-oriented path on Intel hardware and PyTorch/Triton as a strong portability/productivity baseline for cross-vendor HPC stencil development.