Papers for

hardware test engineers

Papers whose findings have a practical use for this group, as judged from the abstract. Open a paper to read what it means in practice.

Technique detects faults effectively in cluster-based FPGA chips

Detection of Single Stuck-at and Bridging Faults in Cluster-based FPGA Architectures

Abstract: This paper presents a new technique for detecting single stuck-at and bridging faults in cluster-based FPGA architectures, using same set of test vectors generated by a test pattern generator circuitry. This technique is based on configuration of logic elements using test logic structure and the outputs of two separated logic elements are compared to detect a fault. To do this, block under test, TPG and output response analysis circuitry are generated in FPGAs. The configurations of test pattern generation, block under test and output response analysis are also discussed in this paper. The novelty lies in the fact that the same set of test vectors can detect all the stuck-at as well as bridging faults if the test vectors are applied in a particular sequence and analyzing the output results. We presented a detail analysis of results to detect faults as well.

Mon 26 OctHardware Architecture

The gist

Detecting faults in FPGAs, which are chips that can be programmed for different tasks, is important to make sure they work correctly. This paper shows a method to find two types of common faults using the same set of test inputs in a clever way. The authors use special logic setups inside the FPGA to compare outputs and identify errors without needing different tests. Their approach helps find faults by analyzing outputs after applying test sequences, making testing simpler and more efficient.

Open → 2610.35026v1