Papers for

hardware developers

Papers whose findings have a practical use for this group, as judged from the abstract. Open a paper to read what it means in practice.

SpMV speed improves with hierarchical sparse storage on RISC-V

Rethinking Sparse Formats for RISC-V: A Hierarchical Approach to High-Performance SpMV

Abstract: The sparse matrix-vector multiplication (SpMV) algorithm is a fundamental computational kernel of linear algebra and serves as a building block for numerous applications, primarily iterative solvers for systems of linear equations used in scientific and engineering simulations. This paper compares vectorized implementations of the SpMV algorithm across eight established sparse matrix storage formats and proposes a novel modification of the CSR format, Hierarchical CSR (HCSR), which enhances SpMV performance on RISC-V processors. Our SpMV implementations utilize RVV 1.0 intrinsics and are publicly available as an open-source C++ library named RVVLASparse. Computational experiments conducted on SpacemiT K1 and K3 RISC-V boards demonstrate that selecting an appropriate matrix storage format accelerates SpMV computations by an average of 1.6x, while the proposed HCSR format achieves the shortest execution time among all considered formats across a broad class of sparse matrices.

Thu 10 SeptDistributed, Parallel, and Cluster ComputingPerformance

The gist

Multiplying big sparse matrices by vectors quickly is important for many science and engineering problems. The authors tested different ways to store these sparse matrices on RISC-V processors and created a new method called Hierarchical CSR (HCSR). Their new approach makes the multiplication faster than older methods on RISC-V boards. They also shared their code openly for others to use.

Open → 2609.11352v1