hardware design automation engineers

Abstract: Efficient microarchitecture design space exploration (DSE) is critical for optimizing performance, power, and area trade-offs in modern out-of-order processors. While machine-learning-based DSE significantly reduces the cost of exhaustively evaluating large design spaces, existing methods still waste expensive simulations on Pareto-miss candidates that do not improve the Pareto frontier and repeatedly process redundant candidates during iterative exploration. In this paper, we propose PaFeDSE, a Pareto-feedback-guided microarchitecture DSE framework for efficient Pareto search. PaFeDSE leverages Pareto-hit feedback to prioritize candidates likely to improve the frontier and Pareto-miss feedback to suppress exploration of unpromising local regions, while filtering redundant candidates that remain low priority across iterations. Evaluated on SPEC CPU 2017 workloads, PaFeDSE requires up to 49.0% fewer simulations than the strongest prior baseline to reach target hypervolume levels, while achieving a 7.1x reduction in exploration overhead through adaptive candidate filtering.