Papers for

functional programmers designing hardware

Papers whose findings have a practical use for this group, as judged from the abstract. Open a paper to read what it means in practice.

High level hardware description languages offer design ease with some size overhead

Low-level optimizations in high-level HDLs: Is there a benefit?

Abstract: This paper explores the applicability of functional programming to the design of Application-specific Integrated Circuits (ASICs). We investigate the impact of designing ASICs using high-level, abstract Hardware Description Language (HDL) features versus employing low-level optimizations on the area of the synthesized circuits. The aim is to determine whether using low-level optimizations is beneficial and, if so, whether it is worth the added implementation effort. To carry out the investigation, we implement an unsigned bit-serial multiply-accumulate (MAC) unit in 16 different configurations using the functional HDL Clash. We make use of both low-level bit-manipulation techniques as well as Clash's high-level constructs for circuit design. The experimental evaluation shows that some high-level constructs of Clash have negligible influence on the resulting circuit size, suggesting that using the full power of functional programming is a viable approach to hardware design. To evaluate the impact of the used HDL itself, we also implemented versions of the MAC in Verilog. The experiments clearly show that there seems to be an inherent overhead in using Clash compared to Verilog code written by a seasoned engineer.

Tue 29 SeptHardware Architecture

The gist

This paper looks into whether using simpler, high-level programming languages to design computer chips leads to bigger chip sizes compared to using detailed low-level coding tricks. The authors built a small chip component in many ways using a functional programming language for hardware called Clash, and also compared it to a traditional language called Verilog. They found that using Clash’s advanced programming features doesn’t make chips much bigger, which means you can design efficiently at a high level. However, Clash designs still tend to be larger than highly optimized Verilog designs, showing there’s some unavoidable size cost.

Open → 2609.37021v1