Abstract: We propose a low-complexity SVD-based transceiver for zero-padded memory-$1$ ISI channels. Appending a single zero-padding symbol to an $n$-symbol block yields an $n\times(n-1)$ channel matrix with an \emph{exact symmetric tridiagonal Toeplitz Gram matrix}. This structure provides closed-form singular values and vectors, enabling exact SVD precoding and equalization via FFTs without explicitly forming dense SVD matrices. The resulting implementation has $O(n\log n)$ complexity and incurs only a $1/n$ rate penalty. The resulting parallel scalar subchannels enable joint adaptive PAM and power allocation for SER minimization, followed by exact soft-information computation for LDPC decoding. At comparable code rates near $0.945$, simulations show that our proposed scheme outperforms a conventional TX-FFE/RX-DFE system with hard-decision Reed-Solomon (RS) decoding by approximately $5$ dB at FER $10^{-5}$. At high SNR, it achieves nearly the same FER performance as a SOVA-based receiver with LDPC decoding, while replacing trellis-based detection with fast SVD precoding and exact scalar soft-output computation.