Papers for

digital signal processing engineers

Papers whose findings have a practical use for this group, as judged from the abstract. Open a paper to read what it means in practice.

Efficient compression of hardware lookup tables cuts storage needs

Lossless Compression of Lookup Tables for Hardware Applications

Abstract: Large lookup tables are widely used in hardware to store constant-valued arrays for applications ranging from elementary mathematical operations, such as constant-coefficient multiplication and nonlinear function evaluation, to emerging machine learning models, including table-based neural networks (NNs) and Kolmogorov-Arnold networks (KANs). However, storing extensive tables of constant values can lead to excessive hardware costs in resource-constrained edge devices such as FPGAs. In this paper, we propose CompressedLUT, a lossless compression scheme and its decoder hardware architecture for the efficient storage and retrieval of arbitrary data in hardware. Our method combines decomposition, self-similarities, higher-bit compression, and multilevel compression techniques to maximize table size savings without accuracy loss. Its hardware decoder primarily uses addition, arithmetic right shift, and several small lookup tables, ensuring low area and high throughput. We evaluated CompressedLUT on FPGAs by implementing multiple nonlinear functions, constant-coefficient multipliers (CCMs), and KANs at 12-bit resolution. CompressedLUT is available as an open-source tool.

Tue 29 SeptHardware Architecture
The gist
Storing large lookup tables in hardware like FPGAs can use a lot of space, which is a problem for small devices. The authors propose CompressedLUT, a way to shrink these tables without losing any data, using clever steps to find patterns and compress effectively. They also designed a simple hardware decoder that is fast and takes up little space. Their tests show it works well for mathematical functions and certain neural networks. The software to do this is publicly available.
Open → 2609.36634v1

Quantum computers perform FIR signal filtering using state-space methods

State-Space-Based FIR Filtering on a Quantum Computer

Abstract: Many signal processing tasks require intensive computations. Quantum computing promises to accelerate certain tasks, but algorithms must be designed around the limitations of quantum mechanics. This paper provides a quantum implementation of finite impulse response (FIR) filters, which are a widely used tool in classical signal processing. The filter can be parallelized and composed as part of larger quantum algorithms, with potential for speedups using quantum amplitude estimation and future fault-tolerant quantum hardware. To accomplish these properties, we introduce a state-space framework wherein sample-based signal processing is performed with unitary quantum circuits. We present the quantum delay gate as the quantum analog of the delay line in discrete-time signal processing. Unitary circuits intrinsically describe lossless systems, but we also implement lowpass and other bounded filters by emulating a projection operator. The FIR filter implementation is tested and demonstrated with a quantum circuit simulator.

Thu 17 SeptSound
The gist
Many signal processing tasks need a lot of computing power, and quantum computers might speed these up. The authors created a way to run finite impulse response (FIR) filters—a common tool in signal processing—on quantum computers using unitary circuits. They introduce a special quantum delay gate that acts like delay lines in digital signals and show how to build lowpass and other filters in this framework. They tested their method using a simulator that mimics quantum circuits.
Open → 2609.20331v1