Papers for

data center hardware teams

Papers whose findings have a practical use for this group, as judged from the abstract. Open a paper to read what it means in practice.

Toki profiles memory performance on FPGA systems with many RISC-V cores

Toki: Profiling HBM Performance on FPGA Systems with RISC-V Soft Cores and PCIe Host DMA Traffic

Abstract: Programmable RISC-V soft cores are becoming more widespread in data-center scenarios, making it crucial to design efficient systems that deploy them on FPGA chips with HBM memory. Toki, released as open source, is the first hardware-software framework that enables profiling the performance of HBM on FPGA accelerator cards by jointly considering (i) the execution of workloads on RISC-V soft cores instantiated on the FPGA and (ii) the injection of memory traffic from the host system via DMA over PCIe, providing insights that cannot be obtained with synthetic traffic generators alone. Extensive experiments target an AMD Alveo U55C card, deploying up to 60 RISC-V compute cores and stressing its HBM2 memory through real-world applications and microbenchmarks with user-defined access patterns. Results showcase how Toki can effectively profile the impact on HBM performance of the compute cores' organization, the workload's memory access patterns, data locality, contention over the memory controllers, and host traffic.

Tue 22 SeptHardware Architecture
The gist
High-bandwidth memory (HBM) on FPGA accelerator cards plays a big role in speeding up data center tasks. The authors created Toki, a system that measures how this memory performs when running many RISC-V soft processor cores on an FPGA while also handling data from a host computer over PCIe. This helps reveal how different factors like core arrangement, memory access methods, and traffic from the host affect speed and efficiency. Their tests used a real AMD FPGA card and showed how real-world applications stress the memory differently than simple test patterns.
Open → 2609.26551v1

StreamNTT performance tested on open source Verilog routing toolchain

Benchmarking StreamNTT with a Verilog-to-Routing Toolchain

Abstract: As post-quantum cryptography algorithms move toward large-scale data center deployment, hardware acceleration of their computational bottleneck, which is the number theoretic transform (NTT), has gained increasing attention. StreamNTT, a high-level synthesis- and field-programmable gate array-based accelerator, achieves state-of-the-art throughput through various optimization techniques. However, its reliance on a commercial tool and a device makes direct comparisons difficult for researchers without access. We address this by building StreamNTT on an open-source Verilog-to-Routing toolchain, which achieves similar digital signal processing and multiplier usage. Significant differences in internal memory utilization indicate that further memory-level optimization is needed to approach commercial tool performance.

Sat 19 SeptHardware Architecture
The gist
StreamNTT is a tool that speeds up key calculations used in new types of encryption meant to be safe from quantum computers. The original version needed special commercial software and hardware, which made it hard for others to compare or use. The authors recreated StreamNTT using an open-source toolchain and found it uses similar amounts of digital processing parts and multipliers. However, it uses memory differently, showing that more work is needed to match the commercial tool's efficiency.
Open → 2609.23116v1